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Logic synthesis
Results: 291

#	Item
151	SNPS[removed]10-K Add to Reading List Source URL: synopsys.com Language: English - Date: 2014-12-15 13:24:22 Integrated circuits Hardware verification languages Synopsys Hardware description language Electronic system-level design and verification Signoff Logic synthesis Integrated circuit design SystemVerilog Electronic engineering Electronic design automation Electronic design
152	Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-02-27 22:53:37 Diagrams And-inverter graph Logic synthesis Field-programmable gate array Directed acyclic graph Algorithm Heuristic function Electronic engineering Electronic design automation Electrical engineering
153	DAG-Aware AIG Rewriting A Fresh Look at Combinational Logic Synthesis Alan Mishchenko Satrajit Chatterjee Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-08 11:02:22 Digital electronics Electronic design Logic in computer science And-inverter graph Logic synthesis Field-programmable gate array American International Group Directed acyclic graph Logic gate Electronic engineering Electronic design automation Formal methods
154	Microsoft Word - fpga061s-mishchenko1.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-12-16 19:04:56 Digital electronics Electronic design And-inverter graph Field-programmable gate array Logic synthesis Static timing analysis Placement Logic optimization Propagation delay Electronic engineering Electronic design automation Formal methods
155	Logic Synthesis for Regular Layout using Satisfiability Marek Perkowski and Alan Mishchenko Department of Electrical and Computer Engineering Portland State University Portland, OR 97207, USA [mperkows, alanmi]@ece.pdx.e Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2002-05-01 01:40:28 Theoretical computer science Electronic design automation Diagrams Formal methods Lattice theory Binary decision diagram Boolean satisfiability problem Logic synthesis Lattice Abstract algebra Mathematics Boolean algebra
156	Improvements to Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-08-09 21:17:37 Formal methods Logic in computer science NP-complete problems And-inverter graph Diagrams Boolean satisfiability problem Satisfiability Logic synthesis Automatic test pattern generation Electronic engineering Theoretical computer science Electronic design automation
157	Fast Heuristic Minimization of Exclusive-Sums-of-Products∗ Alan Mishchenko and Marek Perkowski Department of Electrical and Computer Engineering Portland State University, Portland, OR 97207, USA [alanmi,mperkows]@ee.p Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2001-07-16 02:56:52 Electronic design Electronic design automation Boolean algebra Logic optimization Karnaugh map Logic synthesis Minimisation Cube Electronic engineering Design Digital electronics
158	Applying Logic Synthesis for Speeding Up SAT Niklas Een, Alan Mishchenko, Niklas S¨ orensson Cadence Berkeley Labs, Berkeley, USA. EECS Department, University of California, Berkeley, USA. Chalmers University of Technol Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-03-20 02:33:25 Theoretical computer science Conjunctive normal form And-inverter graph Science Mathematics Circuit Canonical form Boolean network Logic Electronic design automation Formal methods
159	LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-09 02:20:06 Boolean algebra Diagrams Field-programmable gate array Binary decision diagram Lookup table Xilinx Multiplexer Artificial neuron Function Computing Mathematics Electronic engineering
160	Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-09-11 21:52:58 Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering Electronic design automation Formal methods

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